1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming the gate terminal of a device.
2. Description of Related Art
In the manufacturing of deep sub-micron circuits, line width, contact area and the junction depth of a device are all reduced because of the need for higher circuit capacity. In order to increase the reliability of devices and to decrease contact resistance so that RC delay is reduced, a metal silicide layer is usually formed on top of the conventional gate polysilicon layer. Since no photolithographic operation is required to form the silicide layer, the step of forming the metal silicide layer is also referred to as a self-aligned silicide (Salicide) process. At present, titanium silicide (TiSi.sub.x) is the most widely used material for forming a self-aligned silicide layer because titanium silicide not only has a lower resistance but also can be more readily controlled in the manufacturing process.
However, as the line width of the polysilicon gate continues to shrink, a narrow-line line effect becomes dominant. The narrow-line effect is generally used to describe the exceptional contact stress created between a metal silicide layer and its underlying polysilicon gate layer. The narrow-line effect also includes the increase in sheet resistance resulting from a smaller number of nucleation sites in the metal silicide layer due to a reduction in gate line width, thereby affecting the operational efficiency of the gate terminal.
In light of the foregoing, there is a need to provide an improved method of forming the gate of a device.